This application claims the benefit of Japanese application No. 11-178724, filed Jun. 24, 1999, which is hereby incorporated by reference.
The present invention relates generally to a semiconductor integrated circuit device, and more particularly to the technology associated with the structure and layout of a semiconductor integrated circuit, which is created particularly in consideration of the protection from electrostatic breakdown and the compatibility with automatic layout.
In semiconductor integrated circuit devices, the percentage of automatic designing has been increased for a protection circuit in input/output circuits and internal circuits by locating electrodes, loop wires and input/output circuits, and internal circuits from a peripheral region to a central region in order, and by connecting respective power wires, which extend from the electrodes to the internal circuits, to the loop wires on route (see FIGS. 5A and 5B, and Description of Prior Art in JP-A-5-145015). The protection circuit may be formed between a power and a ground lines associated with the input and output circuit (see FIGS. 6A and 6B), or formed through input and output lines (prior art examples shown in JP-A-10-74893, and so on). Also, a protection circuit formed in an elongated region is also known for enhancing the protection ability to the electrostatic breakdown (see JP-A-6-224372).
Among semiconductor integrated circuit devices as mentioned, detailed description will be given on an IC chip 1, the structure of which is illustrated in FIGS. 5A and 5B. FIG. 5A generally illustrates the layout of the IC chip 1, and FIG. 5B is a schematic diagram illustrating a main portion of the IC chip 1 in perspective view. FIGS. 6A and 6B in turn illustrate the structure of a protection circuit in input/output circuits of the IC chip 1, wherein FIG. 6A is a schematic vertical sectional view, and FIG. 6B illustrates an equivalent circuit which is assumed in consideration of a discharge to ground terminal or powering terminal. Further, FIGS. 7A and 7B illustrate equivalent circuits which are assumed in consideration of a discharge to grounded terminals and so on over the entire circuit, wherein FIG. 7A illustrates a circuit diagram in favor of spatial relative positions of components, whereas FIG. 7B illustrates a circuit diagram in favor of discharge paths through the components.
The IC chip 1 is generally formed in the shape of a quadrilateral thin plate by dicing a semiconductor substrate such as a silicon wafer having integrated circuits formed on the main surface thereof. The layout of the integrated circuit is designed in such a manner that a large number of electrodes 2, 3, 4 for external connections such as bonding pads are located in peripheral regions along the four sides. A majority of the electrodes are assigned to I/O pads 2 for signal input/output, and some of the remaining electrodes are assigned to a Vdd pad 3 for power supply and a GND pad 4 for grounding, which are formed in pair, in order to supply operating power to an internal circuit 8 and an I/O circuit 7 from the outside. Inside the electrodes 2, 3, 4, the integrated circuit includes a Vdd line (loop wire) 5 made of aluminum or the like and formed in a loop-like wiring pattern, and a GND line (another loop wire) 6 which makes a round inside the Vdd line 5. Further, the I/O circuit (input/output circuit) 7 is disposed between and underlying these loop wires 5, 6. In a remaining central portion of the IC chip, the internal circuit 8 is disposed.
In addition, an outer Vdd line 5a extends inwardly from the Vdd pad 3 (electrode for power supply) and is connected to the Vdd line 5 (loop wire associated therewith); an intermediate Vdd line 5b extends inwardly beyond the GND line 6; and an inner Vdd line 5c further extends or branches from the intermediate Vdd line 5b, and is eventually connected to the internal circuit 8. These Vdd lines 5a-5c complete one of paired power wires. The other of the paired power wires is completed by an outer GND line 6a which extends inwardly from the GND pad 5 (electrode to the ground) beyond the Vdd line 5 and is connected to the GND line 6 (loop wire associated therewith); an intermediate GND line 6b which extends further inwardly from the GND line 6; and an inner GND line 6c which further extends or branches from the intermediate GND line 6b, and is eventually connected to the internal circuit 8.
Among these power wires, the outer Vdd line 5a, the intermediate Vdd line 5b, the outer GND line 6a, and the intermediate GND line 6b generally present substantially linear simple patterns. Also, these power wires and loop wires 5, 6 are thicker than branching lines such as the inner Vdd line 5c and the inner GND line 6c. It should be noted that while FIG. 5B illustrates the power lines 5a, 5b, 6a, 6b as if they were bonding wires, this is because the illustration emphasizes the three-dimensional appearance to clearly show how connections are made. Actually, they are often formed of multi-layer wiring patterns.
In the region of the I/O circuit 7 (see FIG. 6A), a number of wells are generally formed for element separation, and transistors and so on may be fabricated therein for driving a variety of input/output signals. For receiving the driving power for the transistors and for protecting the components from an unwanted reverse bias and so on, connections are made to positive and negative supply voltage lines, a ground line, and so on. At the connected locations, diodes 7a are explicitly or parasitically provided by PN junctions or the like. The diodes 7a may be connected to the overlying Vdd line 5 or GND line 6. Then (see FIG. 6B), the diodes 7a or equivalent back-flow blocking means, capacitors 7b parasitically formed thereby, and so on cause surge noise introduced into signal input/output lines, the GND line 6 and so on to promptly escape to the Vdd line 5 or the like.
Further, the internal circuit 8 is formed with a number of logical circuits, digital or analog signal processing circuits, and so on, corresponding to a variety of applications, wherein the operating power required thereby is supplied through thin wires branched off from the inner Vdd line 5c and the inner GND line 6c.
A majority of individual circuits within the IC chip 1 is automatically laid out using a design aid tool such as a computer. Specifically, when data such as the chip size, the number of pads and so on are given as design parameters, the positioning of the I/O pads 2 and so on, the routing of the Vdd line 5 and the GND line 6 are automatically determined. Likewise, for the power lines 5a-5c and 6a-6c, once data on the positioning of the Vdd pad 3 and the GND pad 4 are given as design parameters, the wiring from the pads 3, 4 to the internal circuit 8 is automatically determined from the design parameters. Further, the other circuits 7, 8 and branching and routing of power wires connected thereto are also automatically laid out based on other design parameters corresponding to particular applications.
With a semiconductor integrated circuit device having a layout as described above (see FIGS. 5A and 5B), when consideration is made to an electrostatic discharge to a ground terminal connected to the ground electrode 4 and a power terminal connected to the power electrode 3, the input/output circuit 7 is located closer to the power supply electrodes 3, 4 than the internal circuit 8 from a spatial point of view (see FIG. 7A), whereas the internal circuit 8 is located closer to the power supply electrodes 3, 4 than the input/output circuit 7 from a viewpoint of electric or electronic circuit (see FIG. 7B), when viewed in the equivalent circuits. For this reason, parasitic resistances 5d, 6d formed of resistance components, inductance and so on distributed over the loop wires 5, 6 act on the input/output circuit 7 larger than on the internal circuit 8, causing surge noise generated by a discharge or the like and introduced into the electrode 4 and so on to leak more or less into the internal circuit 8. In many cases, however, such leakage has so far been accommodated by the layout described above (see FIGS. 5A and 5B).
Unfortunately, since increasingly advanced miniaturization of the internal circuit results in more and more reduced resistance of the internal circuit, the internal circuit would not be sufficiently protected from an electrostatic discharge or the like to the ground terminal and powering terminal, unless some appropriate actions are taken. This would be a significant inconvenience.
To solve this problem, it is contemplated to utilize the technique described in JP-A-6-224372 which, however, is not compatible with a layout based on loop wires since JP-A-6-224372 relies on the existence of a starting end on a power wire. In addition, since this technique requires setting of the length of an area in which a protection circuit is formed, the number of required parameters is increased, thus making the technique inappropriate to automatic designing.
It will therefore be appreciated that there exists a technical challenge in how to enhance the protection capability for the internal circuit against the electrostatic breakdown without limiting the convenience of the automatic layout.
The present invention has been made to solve the problem mentioned above, and its object is to provide a semiconductor integrated circuit device which is highly resistant to the electrostatic breakdown and also compatible with automatic designing.
A semiconductor integrated circuit device in a first aspect of the present invention made to solve the problem mentioned above comprises a number of electrodes formed of bonding pads, bumps or the like, a plurality of loop wires such as power wires, ground wires and so on, a number of input/output circuits, and an internal circuit having all or part of circuit elements smaller than those in the input/output circuits. These components are arranged in order from a peripheral region to a central region of a substrate. Within the power wires originating from a pair or a plurality of the electrodes assigned for power supply and routed to the internal circuit directly or indirectly through associated loop wires, paired power wires such as those for powering or grounding, or positive and negative power wires each have a path from an associated one of the electrodes to the internal circuit through an associated loop wire, wherein one of power wires within the pair is connected to the internal circuit at a location closer to the electrode associated with the other power wire than to the electrode associated with the one power wire.
According to the semiconductor integrated circuit in the first aspect as described above, the power wire from the power supply electrode to the internal circuit is not only connected halfway to the loop wire as previously mentioned, but also passes the entirety or a portion of the loop wire from the connecting point therewith, and is separated from the loop wire at a location close to the connecting point of the other power wire with the associated loop wire near the electrode associated with the other power wire in the pair.
With the foregoing structure, the connecting positions of the paired power wires with the internal circuit are replaced with each other, making use of the loop wires. As the result of the replacement, an input/output circuit existing between the replaced connecting positions is moved to a location between the internal circuit and the power supply electrode on the power wire or power supply path, even from a viewpoint of the circuit.
Thus, even if surge noise or the like is introduced into the power supply electrode, a protection circuit in the replaced input/output circuit acts to let the noise to escape therethrough, thereby reducing the amount of the surge noise or the like which may reach the internal circuit. And, such a change of layout is achieved without no new design parameter, so the automatic layout is useful.
It is therefore possible, according to the first aspect of the present invention, to realize a semiconductor integrated circuit device which is highly resistant to electrostatic breakdown and also compatible with automatic designing.
A semiconductor integrated circuit device in a second aspect of the present invention made to solve the problem mentioned above comprises a number of electrodes formed of bonding pads, bumps or the like, a plurality of loop wires including power wires, ground wires and so on, a number of input/output circuits, and an internal circuit having all or part of circuit elements smaller than those in the input/output circuit. These components are arranged in order from a peripheral region to a central region of a substrate. Within the power wires originating from a pair or a plurality of the electrodes assigned for power supply and routed to the internal circuit directly or indirectly through associated loop wires, paired power wires such as those for powering or grounding, or positive and negative power wires each have a path from an associated one of the electrodes to the internal circuit through an associated loop wire, wherein the pair of power wires are routed such that a connecting point of the one power wire from the associated loop wire to the internal wire corresponds to a connecting point of the other power wire from the associated loop wire to the internal circuit, and the connecting point of the other power wire from the loop wire to the internal circuit corresponds to a connecting point of the one power wire from the associated electrode to the associated loop wire.
According to the semiconductor integrated circuit device in the second aspect as described above, the power wire from the power supply electrode to the internal circuit passes the entirety or a portion of the loop wire from the connecting point therewith, and is separated from the loop wire at a location close to the connecting point of the other power wire with the associated loop wire near the electrode associated with the other power wire in the pair, so that the connecting positions of the paired power wires with the internal circuit are replaced with each other, making use of the loop wires. Furthermore, given parameters required to determine the connecting positions of the power supply electrodes to the loop wires, the connecting points of the power supply electrodes to the circuit wires are automatically determined because of their correspondence to the parameters.
Thus, in addition of the replacement of connecting positions of the paired power wires with respect to the internal circuit making use of the loop wires, the correspondence relationship becomes apparent when the replacement is performed. In addition, since the respective connecting positions remain substantially unchanged except for the replacement, differences in parameters and so on required for the automatic layout are eliminated by automatical processing such as copying, swapping or the like of preset parameter values, thus making it easier to change an existing design tool and so on.
It is therefore possible, according to the second aspect of the present invention, to readily realize a semiconductor integrated circuit device which is highly resistant to electrostatic breakdown and also compatible with automatic designing.
A semiconductor integrated circuit device in a third aspect of the present invention made to solve the problem mentioned above is a modification to the semiconductor integrated circuit device in the second aspect, wherein the power wires formed in pair, or at least portions of the power wires which run across the inner and outer loop wires, are offset from each other in regions corresponding to the connecting positions, i.e., the connecting position from the outer loop wire to the internal circuit and the connecting position from the associated electrode to the inner circuit wire, such that the power wires can extend in parallel.
According to the semiconductor integrated circuit device in the third aspect as described above, the paired power wires are offset so as to run in parallel in such a region in which the paired power wires would otherwise overlap with each other, thus making it possible to eliminate additional wiring layers and an insulating layer sandwiched therebetween for mutual insulation, a increase in semiconductor manufacturing steps required for such additional wiring layers, and a consequently increased cost. Since the amount of offset can be uniquely predefined on the basis of a required distance for insulating the pair of parallelly running power wires, the offset power wires would never damage the corresponding relationship of the connecting positions or impede the automatic layout processing.
In this way, the connecting positions of the paired power wires with the internal circuit are replaced with each other, making use of the loop wires, and since the replacement does not cause the power wires to overlap, additional wiring layers are not required.
It is therefore possible, according to the third aspect of the present invention, to readily and economically realize a semiconductor integrated circuit device which is highly resistant to electrostatic breakdown and also compatible with the automatic designing.